ABSTRACT
System efficiency of conventional photovoltaic (PV) systems is adversely affected by mismatches among series connected cells, submodules, and modules. Module-level power converters, often referred to as dc optimizers, mitigate mismatch related losses by performing maximum power point tracking (MPPT) locally, at the PV module level. However, dc optimizers must process all PV power and in the process they introduce insertion losses even when there are no mismatches. Differential power processing (DPP) architectures mitigate mismatch-related losses while processing only a fraction of the PV system rated power, and without insertion losses.
This thesis is focused on the design, implementation and evaluation of submodule integrated converters (subMICs) in the isolated-port DPP architecture. Using a simple voltage balancing approach where voltage reference is set by the shared isolated port, the subMICs can be controlled autonomously in a distributed manner, without the need for a central controller or communication among units. A custom CMOS controller integrated circuit is developed, which demonstrates voltage-balancing control, power limiting, and protection features on prototype subMICs based on bidirectional flyback converters.
A system prototype, including three subMICs, is placed in the junction box of a standard 72- cell PV module, replacing conventional bypass diodes. Performance of the subMIC-enhanced PV module is evaluated through laboratory and outdoor field experiments. Experimental results show greater than 99% module-level efficiency under 25% mismatch, using subMICs rated at one third of the PV power. A performance/cost analysis is performed to select the optimum subMIC design for a given PV system, resulting in best energy-yield improvements at minimum incremental cost.
ISOLATED-PORT DPP SUBMODULE INTEGRATED CONVERTER (SUBMIC)
Figure 2.1: Isolated PV-to-bus architecture.
Figure 2.1 shows a single PV module with three subMICs forming the isolated PV-to- bus architecture. The subMICs are isolated bi-directional DC-DC converters. It is assumed that Vstr is controlled to be at MPP by the central inverter.
Figure 2.4: Bi-directional yback topology used for the subMIC power stage with MOSFET switches.
The yback converter is a buck-boost type converter with isolation due to the yback transformer present in the topology. It is easily modified to be a bi-directional converter as shown in Figure 2.4. The topology uses only two semiconductor switches and a single magnetic component, which makes it attractive as a cost effective solution. The drawbacks of the topology is that the semiconductor is exposed to high voltages during switching of transition.
DESIGN REALIZATION OF SUBMICS
Figure 3.3: Diagram of core and winding structure with key design geometries shown.
Winding of the magnetics are designed on the copper layers of a PCB. The design can have multiple turns of winding on a single PCB layer or have multiple PCB layers for multiple turns. Due to the small geometry of the core, single turn per PCB layer is used for the prototype design. Even a two turn per layer winding would be hard to design due to the vias required near the center of the winding. It would only be possible to fit one or two minimal sized vias. The winding structure relative to the core are shown in Figure3.3.
Figure 3.9: Planar PCB layout.
The planar winding PCB layout is shown in Figure 3.9. The routing between the winding layers are done through multiple vias on the outer edges. End terminations are made so that it could be easily placed and removed from the subMIC board.
Figure 3.11: Structure of the subMIC prototype with the controller IC.
A single controller IC can be used to integrate many of the functions required for the subMIC. The prototype subMIC controller IC includes the key functions for voltage balancing control, power limiting, and modes for loss optimized controls. It also includes a voltage to PWM conversion feature for dual use as secondary side voltage sensing IC. SubMIC board with the IC controller is shown in Figure 3.11.
SUBMIC PERFORMANCE EVALUATION
Figure 4.1: Measured subMIC power stage efficiency with the 22-442 magnetics (top) and the 20-442 (bottom).
For the measurements, the output of a single converter is fixed to 12.5 V. Then, the input voltage is increased while the converter is operated in closed-loop. The converter controls are set to have a minimum duty cycle of 15% and maximum of 48%. With this setup, the duty cycle saturates around 25 W of power. For the comparison, ELT22 and ELT20 cores with the 442 winding setup are used. Results are shown in Figure 4.1.
Figure 4.11: Secondary side operation verification.
The secondary side mode is set by ENp=0 and ENs=1. The function is verified by comparing the reference voltage on Hduty to the tri signal. It is confirmed that the PWM output works as expected. The result is shown in 4.11. The slight skew seen in the PWM is from the 10 nF load connected to the output. In the prototype, the output of the PWM will see a much smaller load.
SYSTEM PERFORMANCE EVALUATION
Figure 5.1: Current biasing a PV substring.
The main focus of the indoor experiments is to evaluate the system performance under a controlled environment. Indoor experiments are performed at a module level with three substrings tied to the subMIC board. The PV substrings are biased with current sources that emulate various levels of insolation. Figure 5.1 shows how the bias would equivalently look like if biased at the string level.
Figure 5.4: PV sweep of power limited subMICs under 80% mismatch (top) and 90% mis- match (bottom).
When the subMIC power limit is not reached, the system operates in the same manner as the system with full-power rated subMICs. When the power limit is hit, the system characteristic changes. Figure 5.4 shows the PV curves under extreme mismatches. The 80% mismatch corresponds to 600 mA biasing and 90% mismatch corresponds to 300 mA bias current.
DESIGN OPTIMIZATION OF SUBMICS FOR DPP PV SYSTEMS
Figure 6.1: Block diagram of improved subMIC IC design with the rev. 2 subMIC core reused.
A conceptual improved subMIC IC design (rev.3) and the peripheral circuits are shown in Figure 6.1. The new design eliminates all extra ICs with the cost of extra gate driving circuitry for the secondary side. Next, planar winding designs can be integrated into the main PCB. This will reduce the manufacturing cost, but it would significantly increase the overall PCB cost for the prototype design.
Figure 6.6: Optimal design selection scenario.
The cost/performance plot in Figure 6.6 shows how the designs would distribute rela- tive to PV module cost (CostPV ) slope and the loss percentage of the conventional system (Lossconv). Improvement cannot exceed the system loss from the conventional system, hence the designs are shown to the left of the loss line. Designs below the PV module cost line are which the cost of the subMICs are justified for the performance improvement. A measure is defined to quantify the cost justification: SubMIC Figure Of Merit (SFOM).
Figure 6.7: Block diagram of optimal design selection.
The ageing scenarios have a uniform, but weak power mismatch distributed among the PV cells. On the other hand, shading scenarios have a more stronger and spatially localized power mismatch. Two types of evaluations are performed: ageing and shading scenarios. For each scenario, different PV systems with varying module power rating and setup are used. Figure 6.7 shows the block diagram of the evaluation and optimization process.
Figure 6.24: Performance improvement versus subMIC power rating to module rating.
Furthermore, the minimal cost contour should monotonically increase, hence design #2 is discarded. As a result, we are left with 5 design candidates for possible optimal designs. Further design set reduction is difficult since the performance improvement to power rating relationship can be highly non-linear. This is shown in Figure 6.24 where the power rating is normalized by the module power for the shading scenarios.
CONCLUSIONS
This dissertation presents design and optimization of sub-module integrated converters (subMICs) in the isolated-port differential power processing (DPP) photovoltaic (PV) system architecture. Due to the series connection of PV cells, conventional PV systems based on string-level or system-level power electronics are prone to significant performance degradation related to mismatches among the PV cells caused by partial shading, temperature gradients, and tolerances in cell parameters.
Distributed power processing using high-effciency switched-mode power power converters at the PV module or sub-module level can be used to mitigate such performance degradation. Improving the energy-capture performance of a PV system while minimizing the cost overhead associated with power converters is a challenge. PV system installations are not all alike, ranging from relatively small rooftop residential systems to large commercial or utility-scale systems. In particular, residential systems are very often subject to varying partial shading conditions caused by nearby trees or roof features.
In commercial or utility-scale systems, mismatch conditions are present due to tolerances parameters (which tend to grow as the system ages), temperature gradients, and inter-row shading. Performance of distributed power electronics architecture in general, and DPP architectures in particular, depend on the system mismatch scenario. Hence, it is desirable to have the converter designs optimized for each setup to maximize performance improvements while reducing cost. In the isolated-port DPP architecture, which is the focus of this thesis, optimizing the subMIC design requires understanding of the DPP architecture, converter design and control issues, as well as the PV system installation environment.
An advantage of the DPP architecture is that the DPP subMICs can provide for power matching among mismatched PV substrings, while processing only a fraction of the full PV power. This allows the use of low power rated subMICs, while the performance of the system is not critically sacrificed. Also, the converter effciency does not critically impact the system energy-capture performance, in contrast to full power processing architectures such as DC optimizers, where the converter effciency is simply a multiplicative factor in the overall system effciency.
Source: University of Colorado
Authors: Beomseok Choi