Power optimization is a very important and challenging step in the physical design flow, and it is a critical success factor of an application-specific integrated circuit (ASIC) chip. Many techniques are used by the place and route (P&R) electronic design automation (EDA) tools to meet the power requirement.
In this paper, we will evaluate, independently from the library file, the impact of redefining the max transition constraint (MTC) before the power optimization phase, and we will study the impact of over-constraining or under-constraining a design on power in order to find the best trade-off between design constraining and power optimization.
Experimental results showed that power optimization depends on the applied MTC and that the MTC value corresponding to the best power reduction results is different from the default MTC. By using a new MTC definition method on several designs, we found that the power gain between the default methodology and the new one reaches 2.34%.
THE BASIC CONCEPT OF POWER CALCULATION AND OPTIMIZATION
The energy consumed in an integrated circuit (IC) can be split into two main branches: A static power dissipation related to the logical states of the circuit. In CMOS logic, the leakage current and subthreshold current are the only sources of static power dissipation. A dynamic power dissipation, which is caused by the switching activity of the circuit. A higher operating frequency leads to more frequent switching activities in the circuit and results in increased power dissipation.
MAX TRANSITION VARIATION IMPACT ON POWER OPTIMIZATION (CASE STUDY)
We applied Flow 1 on Test Case 1 (Figure 1), the characteristics of which are summarized in Table 1. We evaluated for an MTC interval of [0 ps–5000 ps], the corresponding power reduction achieved after optimization. The graph in Figure 2 summarizes the results. We noticed that the power dissipation is reduced rapidly as MTC increases until 1000 ps. Then, it still decreases slowly until it reaches 4000 ps. Then, the power reduction is constant. This means that, in order to achieve the optimum power reduction, the MTC should at least be equal to this threshold value.
We deduced from the results shown in Table 4 and Figure 5 that, with the default MTC, the average power gain is 38.3%, while it reaches 43.3% with the newly generated MTC. Additionally, we noticed that the timing is better in most cases for both setup and hold (Figures 6 and 7).
By evaluating the effect of max transition constraint on power optimization over various designs and technological nodes, we demonstrated experimentally that, in order to reduce the power consumption of a System on Chip (SoC) optimally, one should evaluate different values of max transition to well constrain the design before starting power optimization. We also showed that, by adopting this method of max trans evaluation, the gain in power reduction reaches 2.35% in some designs.
This paper proved the existence of a good MTC value (MTCn) that gives better power reduction results, which is different from the default MTC (MTCd). More work can be done to reduce the runtime of finding the MTCn value by using more efficient analytical techniques other than the dichotomy approach adopted in this paper. Additionally, another dimension may be explored by studying the relationship between the design node, size, structure, and MTC, which may lead to a direct method or equation to find the best MTC without running any experiments.
Source: University Mohammed
Authors: Mohamed Chentouf | Alaoui Ismaili Zine El Abidine