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Implementation of a VBR MPEG-stream Receiver in an FPGA

Nowdays, the transmission of digital TV-signals tends to move towards more untraditional medias, such as TCP/IP networks.

This thesis focused on the problems involved in receiving MPEG transport streams of variable bitrate from a TCP/IP connection, such as jitter and clock synchronization. A suggestion for recovering the transport stream is presented along with a implementation for an Xilinx FPGA targeted for a head end device. The implementation was written in a mix of VHDL and Verilog.

Introduction:
A2B Electronics AB is a company that has specialized on creating systems for television operators, which includes a broad range of equipment (head end systems) for receiving and transmitting television and supports various kinds of interfaces (such as several types of DVB, IPTV and ASI for example). One of their systems is called Chameleon, and an example application for such a device is to receive an IPTV stream, process it (select a number of channels) and send to an output for conversion to DVB-C television standard for a cable network.
Source: Linköping University
Author: Liss, Jonathan

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